Previously designed methods for transferring data between two synchronous subsystems operating at low speeds have accurately transferred data. Such speed being relative to the state of the art. In low speed systems, the clock skew or propagation delay between subsystems is negligible since it is only a portion of the entire cycle time. Thus, data transmitted from a first subsystem was stable long enough to allow a skewed clock to capture the data in a state device in the second subsystem while meeting the setup and hold time requirements of a state device in the second subsystem.
Interfacing between subsystems becomes more critical as the operating rates of the subsystems are increased. The operating rate of the subsystems is the rate at which the subsystems transmit and receive data. When such rates are high, there is frequently a problem ensuring that accurate data transmission will occur between subsystems. This problem occurs because data from a source subsystem is not stable long enough to meet the setup and hold time requirements of a destination subsystem's state device. By conventional means, data transmitted from the first subsystem would be stable for at most one clock cycle time. If the clock skew or the propagation delay between two subsystems is greater than this time, it is difficult to guarantee that the destination subsystem will capture the correct data.
One solution to the foregoing data transmission problem is proposed in U.S. Pat. No. 4,811,364 entitled "Method and Apparatus for Stabilized Data Transmission". In one of the preferred embodiments, a clock is forwarded from the source subsystem to the destination subsystem along with the data. The destination subsystem uses the trailing edge of the forwarded clock signal to capture data in its state device. This guarantees that accurate data will be transmitted between two synchronous subsystems.
The one drawback to the foregoing solution is that by utilizing the trailing edge of the forwarded clock to capture data in the destination subsystem's state device, the system becomes sensitive to the pulse width of the clocks. In high speed digital systems, it is difficult to guarantee that the clocks will maintain an even 50%-50% duty cycle. A 50%-50% duty cycle implies that each period of the clock signal will be divided into two equal subperiods, where for one subperiod the clock signal is high and for the other subperiod the clock signal is low. Thus, as clocks are propagated through a system, the pulse widths of such clocks may stretch or shrink. Also, the foregoing solution does not address the problem of transmitting accurate data between two subsystems when propagation delays between the two subsystems exceed the clock cycle times of the subsystems.
While the prior art provides adequate means for transmitting data between two subsystems, there is a need for advancement. In particular, in a high performance synchronous computer system, ensuring accurate data transmission between two subsystems is becoming more difficult as operating rates are increasing. With increased rates of operation, it is imperative to ensure data stability across subsystem boundaries to meet the setup and hold time requirements of a state device in a destination subsystem.